
`include "common_header.verilog"

//  ****************************************************************************
//  File : grm_write_cntl.v
//  ****************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2001-2005 Morethanip
//  MorethanIP GmbH, An der Steinernen Brueke 1, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  ****************************************************************************
//  *            FIFO Write Control          
//  ****************************************************************************
//  Version    : $Id: xgrm_write_cntl.v,v 1.2 2008/01/30 16:01:13 dk Exp $
//  ****************************************************************************

module xgrm_write_cntl (

   reset,
   clk,
  `ifdef USE_CLK_ENA
   clk_ena,
  `endif
   pcs_wren,
   ff_afull,
   ff_wren);
   
input   reset;          //  Global Reset
input   clk;            //  156.25MHz Clock
`ifdef USE_CLK_ENA
input   clk_ena;        // Enable Clock
`endif
input   pcs_wren;       //  FIFO Write Enable Command
input   ff_afull;       //  FIFO Elmost Empty
output  ff_wren;        //  FIFO Read Enable


reg     ff_wren; 

parameter STM_TYP_FAULT  = 1'b0;
parameter STM_TYP_NORMAL = 1'b1;

reg     state; 
reg     nextstate; 

//  FIFO Read Control State Machine
//  -------------------------------

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      state <= STM_TYP_FAULT;   
      end
   else
      begin
      
         `ifdef USE_CLK_ENA
            if(clk_ena == 1'b 1)
            begin
         `endif       
      
                state <= nextstate;   

         `ifdef USE_CLK_ENA
            end
         `endif               
      
      end
   end

always @(state or ff_afull)
   begin : process_2
   case (state)
   STM_TYP_FAULT:
      begin
      if (ff_afull == 1'b 0)
         begin
         nextstate = STM_TYP_NORMAL;   
         end
      else
         begin
         nextstate = STM_TYP_FAULT;   
         end
      end
   STM_TYP_NORMAL:
      begin
      if (ff_afull == 1'b 1)
         begin
         nextstate = STM_TYP_FAULT;   
         end
      else
         begin
         nextstate = STM_TYP_NORMAL;   
         end
      end
   endcase
   end

//  FIFO Command
//  ------------

always @(posedge reset or posedge clk)
   begin : process_3
   if (reset == 1'b 1)
      begin
      ff_wren <= 1'b 0;   
      end
   else
      begin
      
         `ifdef USE_CLK_ENA
            if(clk_ena == 1'b 1)
            begin
         `endif
      
              if (nextstate == STM_TYP_NORMAL & pcs_wren == 1'b 1)
                 begin
                 ff_wren <= 1'b 1;   
                 end
              else
                 begin
                 ff_wren <= 1'b 0;   
                 end
      
         `ifdef USE_CLK_ENA
            end
         `endif
      
      end
   end

endmodule // module grm_write_cntl